Electrical & Electronics Engineering student at Hacettepe University, specializing in Digital System Design, FPGA Prototyping, and RTL Verification. Passionate about computer architecture and developing custom hardware accelerators for high-performance applications.
Python, C++/C, SystemVerilog/Verilog, TCL, Assembly
Vivado, Vivado HLS, Gowin IDE, Spike-ISS (RISC-V), Cadence Xcelium
Openlane Skywater PDK, Altium Designer, Cadence Genus, Cadence Innovus
STM32Cube, ESP-IDF, Raspberry Pi PICO, Arduino, LTSPICE, MATLAB
GitHub, Centos/Ubuntu, Win10
B.Sc. in Electrical & Electronics Engineering | GPA: 2.95
Relevant Coursework: Digital Logic Design, Microprocessors, Computer Architecture, VLSI Design, Embedded Systems
Co-founded SiliCore with EyΓΌp Ertan SaΔdΔ±Ε, establishing Hacettepe University's first VLSI/IC design team from the ground up. Leading the engineering efforts to design an RISC-V microcontroller SoC that includes an AI accelerator, while managing system architecture, top-level integration, and verification flows.
Engineered robust surge protection mechanisms using high-side solid-state switching, ensuring compliance with MIL-STD-1275F standards for military vehicle power characteristics. Designed two variations of gate drive circuitry: a discrete level-shifting driver for high-speed actuation and a transformer-coupled driver for galvanic isolation. Optimized component selection (MOSFETs, BJTs) and verified over-voltage clamping and transient immunity through extensive LTspice simulations.
Within the scope of a 3D scanner project, customizations were performed on ANTMICRO opensource PCBs, considering the software compatibility of embedded systems, camera modules, and FPGA/SoC/ISP solutions. Actively contributed to hardware architecture design and Design for Manufacturing (DfM) processes.
Intern Report βDesigned a 32bit Pipelined ALU with different power modes that van run up to 1.66GHz @Turbo or 180MHz @Lowpower. Verified the RTL design using coverage tests using Cadence Xcelium. Synthesized the design using Cadence Genus. Generated a successful layout Cadence Innovus.
Source & Documentation βDesigned custom PCBs for the UAV payload release mechanism, power distribution, and electronic cut-off systems within a 10-person team. Executed Design for Manufacturing (DfM) by panelizing boards for fabrication at JLCPCB and managed component sourcing through Γzdisan. The team achieved 1st place in Turkey and 5th globally.
View Post βDesigned and fabricated a solid-state Tesla Coil utilizing an ESP32-controlled full-bridge driver topology. Implemented precise MOSFET gate driving and active feedback loops to successfully achieve high-voltage air breakdown.
View Details βWith a team of 4 weβre trying to design a FPGA application for realtime object detection using risc-v and custom acclerators.
View Details βDesigning a custom GPU using FPGA technology to perform realtime Gaussian blur operation using parallel computing techniques and custom acclerators.
Source & Documentation βDeveloping a custom microprocessor architecture with a 5-person team for the Teknofest 2026 Chip Design Competition. Responsibilities include defining the system architecture, designing boot sequencing logic, and executing physical layout implementation.
Team Website β