vorTechx: RISC‑V MCU with AXI Peripherals & LDPC Accelerator
We’re building a single‑clock SoC around the CV32E40P core: AXI4‑Lite peripherals (GPIO, Timer, UART×2, I²C, QSPI), a streaming LDPC accelerator, and a dual‑role DMA for memory↔︎accelerator transfers.
AXI‑centric
One master (CPU) + DMA master, static map to RAM & peripherals.
Streaming LDPC
FIFO bridges, interrupt or polling, DMA for throughput.
Deterministic
Single clock domain, clean reset, clear CDC boundaries.
Open & Measurable
Scripts, reproducible builds, public docs post‑competition.
About
vorTechx is a student team focused on practical digital design: readable RTL, test‑first development, and lightweight tooling. Our goal is a robust MCU SoC that’s simple to integrate and easy to verify.
RV32
CV32E40P core
AXI4‑Lite
Peripherals on static map
DMA
Mem↔︎LDPC transfers
1 Clock
Simplified timing
Architecture
- CV32E40P — I/D OBI → OBI→AXI bridges
- AXI Interconnect — CPU master, DMA master; RAM & peripherals as slaves
- Memory — AXI RAM (IMEM/DMEM), external QSPI flash
- LDPC — stream interface via FIFOs; DMA pulls/pushes
- IRQ — timer/UART/DMA interrupts to core
Single clock domain
Reset‑synchronous
Assertions on AXI
$readmemh boot
Address Map (draft)
0x0000_0000 IMEM (8–32 KB)
0x2000_0000 DMEM (8–64 KB)
0x4000_0000 GPIO
0x4000_1000 TIMER
0x4000_2000 UART0 (general)
0x4000_3000 UART1 (LDPC stream)
0x4000_4000 I2C
0x4000_5000 QSPI
0x4000_6000 DMA (cfg)
Modules
GPIO ×32
AXI‑Lite, DIR/DATA, IRQ
Timer
Compare/IRQ
UART ×2
Gen + Stream
I²C
Master
QSPI
Flash / IO
DMA
AXI‑M + AXI‑Lite
LDPC
Streaming core
Roadmap
Milestone 1 — CPU→AXI→RAM fetch & store; smoke tests
Milestone 2 — GPIO/TIMER on AXI‑Lite; IRQs
Milestone 3 — UARTs + I²C + QSPI
Milestone 4 — LDPC + DMA data path proven
Milestone 5 — FPGA demo + docs
Team
B
Bekir Y.
Integration, AXI/UVM
A
Member A
VHDL Peripherals
M
Member B
LDPC/DMA
Contact
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