Summary

Electrical & Electronics Engineer specializing in Digital Design, FPGAs, and VLSI. Experienced in the full RTL-to-GDSII flow and Heterogeneous SoC design with a focus on ARM-based PS integration and hardware acceleration. Particularly drawn to high-frequency, high-speed digital design — from multi-GHz ASIC timing closure to pushing FPGA platforms past their rated limits. Proven leadership in building custom RISC-V architectures and implementing ML accelerators in FPGA for high-stakes competitions like Teknofest.

Technical Skills

Languages
SystemVerilog Verilog TCL C / Bare-metal C Python Assembly (RISC-V & x86) MATLAB
EDA & ASIC
Cadence Genus Cadence Innovus Cadence Xcelium Vivado / HLS Gowin IDE Quartus / Questa OpenLane (SKY130) Lattice Radiant
Hardware
FPGAs Altium Designer LTspice STM32Cube Oscilloscopes Logic Analyzers
AI & Workflows
Agentic Coding (Claude Code, Cursor) Structured Prompt Engineering Git / Nix Toolchains

Education

Hacettepe University

B.S. in Electrical & Electronics Engineering

Sep 2022 – Jun 2026 · Ankara, Turkey

3.04

GPA / 4.00

Experience

Run-x Mar 2026 – Present

FPGA Design Candidate Engineer (Part-time) · Ankara, Turkey

  • Developing Heterogeneous SoC applications focusing on PS-PL hardware-software co-design and Linux on FPGA (PetaLinux) environments.
  • Multi-platform RTL development across Xilinx (Vivado), Intel (Quartus), and Lattice/Gowin toolchains for vendor-neutral IP portability.
  • Working on RF systems using the JESD204B high-speed serial interface for data-converter-to-FPGA communication.
Aspilsan Energy Nov 2025 – Jan 2026

AR-GE Electronics Design Candidate Engineer · Ankara, Turkey

  • Engineered MIL-STD-1275F compliant surge protection; designed high-side solid-state switching drivers.
  • Optimized component selection (MOSFET/BJT) via extensive LTspice transient simulations.
Clonify Labs Jan 2025 – Feb 2025

Electronic System Design Intern · Ankara, Turkey

  • Customized open-source ANTMICRO PCBs for a 3D scanner project; ensured compatibility with FPGA/SoC.
  • Hardware architecture design and Design for Manufacturing (DfM) using Altium Designer within Linux (Ubuntu/CentOS) workflows.

Projects

Featured Projects
Aug 2025 – Sep 2026

SiliCore – Multi-Platform RISC-V MCU

Teknofest 2026 · 4th of 94 teams Team Captain · 4 FPGA + ASIC
4th / 94 Teknofest 2026 180 MHz on FPGA SKY130 GDSII

Led a 4-person team to 4th place among 94 teams at Teknofest 2026 with a multi-platform RISC-V MCU: the same RTL is prototyped on Gowin & Xilinx FPGAs through automated TCL flows and hardened to GDSII via OpenLane/LibreLane on the SKY130 PDK. Includes a lightweight custom AI accelerator; verified with a UVM environment and Spike-ISS co-simulation.

Team Website →
Jan 2026

PPA-Optimized 32-bit Pipelined ALU

Open Source Solo RTL-to-GDSII
1.66 GHz Turbo mode GPDK45 45 nm

Designed a high-performance, multi-mode 32-bit ALU achieving 1.66 GHz in Turbo mode. Complete RTL-to-GDSII flow using Cadence Genus & Innovus on the GPDK45 (45 nm) PDK. Timing closure and area optimization via custom constraints; functional verification with Cadence Xcelium.

GitHub →
Personal Project

FireCore – RV32IM CPU Running DOOM

Personal Team of 2 Open Source
100 MHz Gowin GW2A ~1.2 FPS DOOM

Co-developed a multicycle RV32IM RISC-V processor in Verilog under a 38-state FSM, running at 100 MHz on a Gowin GW2A FPGA and capable of running the original DOOM from compiled C at ~1.2 FPS. Features a DMA bootloader, 4 KB L1 I/D caches (miss penalty cut from ~20 cycles to ~2), HDMI output, PS/2 & UART input, and a hardware crash-dump debug mechanism.

GitHub → LinkedIn Post →
Other Projects
Sep 2025 – Jun 2026

RISC-V-EYE – Real-time Object Detection

Completed Team of 4 Graduation Project
13 FPS 128×128 TinyDet model Ping-pong buffering

Graduation project — real-time detection system pairing a RISC-V core with a fully custom RTL AI accelerator running the TinyDet model architecture on 128×128 images at 13 FPS. A ping-pong buffer strategy overlaps data transfer with compute. The hand-written RTL was chosen after evaluating Vitis HLS, MATLAB HDL Coder, & hls4ml; models trained with MATLAB Deep Learning Toolbox & Google Colab.

GitHub → LinkedIn Post →
Oct 2024 – Jul 2025

SUAS Competition – Panel PCB Design

1st Turkey / 5th World Team of 10 Hardware Lead

Designed custom PCBs for UAV payload release, power distribution, and electronic cut-off systems within a 10-person team. Panelized for JLCPCB fabrication using Altium Designer. Team achieved 1st place in Turkey and 5th globally.

LinkedIn Post →
2025

ELE475 Solid-State Tesla Coil

Solo Power Electronics Course Project
550 kHz center freq. 40 cm coil

Designed and fabricated a solid-state Tesla coil with an ESP32-controlled full-bridge driver at 550 kHz. Precision MOSFET gate driving and active feedback control for reliable high-voltage air breakdown.

Sep 2025

PixelPipe (customGPU) – Realtime Gaussian Blur

Personal Solo Open Source

Custom FPGA-based GPU performing real-time Gaussian blur using parallel computing and custom hardware accelerators.

GitHub →
Planned
Planned

Fhax – FPGA Overclocking / Speed Validation

In planning Solo FPGA
700 MHz target · Gowin 55 nm 1 GHz target · Agilex 3

Pushing a 55 nm Gowin FPGA toward 700 MHz and an Intel/Altera Agilex 3 toward 1 GHz through aggressive custom timing constraints and clock-tree tuning, to validate one overclocking methodology across process nodes and vendors.

Contact